This patent application claims priority based on a Japanese patent application, H10-295157 filed on Oct. 16, 1998, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory testing device, and more particularly to a memory testing device, a high speed test pattern generator, and a method of generating a plurality of high speed test patterns.
2. Description of the Related Art
The conventional semiconductor memory testing device is shown in FIG. 1. The conventional semiconductor memory testing device comprises a sequence controller 62 and a pattern former 26. The sequence controller 62 controls the generating order of the test patterns for testing a semiconductor memory device. The sequence controller 62 generates an address signal 102 to be output to the pattern generator 26. The pattern generator 26 generates an address pattern signal 106, a data pattern signal 108, and a read write pattern signal 110. The address pattern 106 is input to address input pins of the memory device. The data pattern signal 108 is a data to be written on the memory device. The read and write pattern signal 110 assigns either a write cycle in which the data of the data pattern signal 108 is written on the memory device, or a read cycle in which the data written on the memory device is read out and compared with an expected signal, which is same as the data pattern signal 108.
The sequence controller 62 comprises a vector memory for storing vector instructions which indicate the generating order of the test patterns, a read out controller 14 for reading out the vector instructions from the vector memory 12, a vector cache memory including bank memories 16A and 16C, a pattern multiplexer for selecting either of the bank memories 16A and 16C to output the instructions, and an address expander 22 for generating the address signal 102 based on the instructions input from the pattern multiplexer 20. When the vector instructions read out from the vector memory 12 are being stored into one of the bank memories 16A and 16C, the vector instructions stored in the other of the bank memories 16A and 16C are read out and input to the address expander 22 via the pattern multiplexer 20.
The pattern former 26 comprises a control memory 32 for storing a pattern program to generate each of the test patterns, and a test pattern calculator 36 for generating the test patterns based on the pattern program stored in the control memory 32. The control memory 32 comprises an address control memory 32a, a data control memory 32b and a read and write control memory 32c. The test pattern calculator 36 comprises an XB register for generating an address pattern signal 106, a TP register for generating a data pattern signal 108, a multiplexer, and an XOR circuit. The address signal 102 generated by the sequence controller 62 is input to the address control memory 32a, the data control memory 32b, and the read and write control memory 32c. 
The test pattern calculator 36 generates the address pattern signal 106, the data pattern signal 108, and a read and write signal 110 based on the address signal 102 and the pattern signal stored in the control memory 32c. The pattern signal 106 is calculated based on the instructions read out from the address control memory 32a. The data pattern signal 108 is calculated based on the instructions read out from the data control memory 32b and the read and write control memory 32c. The instructions read out from the read and write control memory 32c are directly output as the read and write pattern signal 110.
FIG. 2 shows instructions stored in the address control memory 32a, the data control memory 32b, and the read and write control memory 32c of the control memory 32. The instruction shown as xe2x80x9cXB less than 0xe2x80x9d indicates that the value of the XB register will be zero in the next cycle. The instruction shown as xe2x80x9cXB less than XB+1xe2x80x9d indicates that the value of the XB register increases by 1 in the next cycle. The instruction shown as xe2x80x9cXB less than XBxe2x80x9d indicates that the value of the XB register does not change in the next cycle. The instruction shown as xe2x80x9cTP less than 0xe2x80x9d indicates that the value of the TP register will be zero in the next cycle. The instruction shown as xe2x80x9cTP less than TPxe2x80x9d indicates that the value of the TP register does not change in the next cycle. The instruction shown as xe2x80x9cTP less than /TPxe2x80x9d indicates that the value of the TP register is inverted in the next cycle. The instruction shown as xe2x80x9cRxe2x80x9d indicates that the read pattern signal is generated in the current cycle, and the instruction shown as xe2x80x9cWxe2x80x9d indicates that the write pattern signal is generated in the current cycle. The instruction shown as xe2x80x9c/Dxe2x80x9d indicates that the pattern signal is inverted for output in the current cycle.
For example, when the value of the address signal 102 input to the pattern former 26 is #0, the instruction read out from the address control memory 32a to the test pattern calculator 36 is xe2x80x9cXB less than 0xe2x80x9d, and the instruction read out from the data control memory 32b to the test pattern calculator 36 is xe2x80x9cTP less than 0xe2x80x9d. When the value of the address signal 102 input to the pattern former 26 is #1, the instruction read out from the address control memory 32a to the test pattern calculator 36 is xe2x80x9cXB less than XB+1xe2x80x9d. In this case the instruction read out from the data control memory 32b to the test pattern calculator 36 is xe2x80x9cTP less than TPxe2x80x9d and the instruction read out from the read and write control memory 32c to the test pattern calculator 36 is xe2x80x9cWxe2x80x9d. The test pattern calculator 36 generates the address pattern signal 106, the data pattern signal 108, and the read and write pattern signal 110 based on the instructions input.
FIG. 3 shows an example of the sequence control instruction stored in the address expander used for generating the address signal 102. The instruction xe2x80x9cNEXTxe2x80x9d of the address #0 indicates that the instruction of the next address, the address #1 in this case, should be output. The instruction xe2x80x9cREPEATxe2x80x9d indicates that the instruction of the current address should be repeatedly output xe2x80x9cnxe2x80x9d times, and following this the instruction of the next address should be output. The instruction xe2x80x9cJNI A nxe2x80x9d indicates that the instruction of the address marked with a label xe2x80x9cAxe2x80x9d should be output xe2x80x9cnxe2x80x9d times, and then the data of the next address should be output. In the example shown in FIG. 3, the address #3 includes the instruction xe2x80x9cJNI A 2xe2x80x9d, and the address #2 is marked with a label xe2x80x9cAxe2x80x9d. The data from the address #2 is output twice at the address #3, and then the data. from the address #4 is output. The instruction xe2x80x9cSTOPxe2x80x9d indicates that the test should be terminated. The address expander generates the address signal 102 in accordance with these sequence control instructions to be output to the pattern former 26.
FIG. 4 shows compressed instructions stored in the vector memory 12. The sequence control instructions are extremely large in practical usage, so high speed memory with a large capacity. is required to store all of the sequence control instructions. Therefore, the sequence control instructions shown in FIG. 3 are compressed for storage in the vector memory 12 in order to save the capacity of the memory. The compressed instructions shown in FIG. 4 are the same as the sequence control instructions shown in FIG. 3. The sequence control instruction xe2x80x9cNEXTxe2x80x9d shown in FIG. 3 is omitted and the remainder of the sequence control instructions are stored in the vector memory 12 with each address of the instruction written next to the respective instruction.
The compressed instruction xe2x80x9cREPEAT 4 #1xe2x80x9d stored in the vector memory address #0 of the vector memory 12 indicates that the sequence control instruction of the address #1 is xe2x80x9cREPEAT 4xe2x80x9d. The compressed instruction xe2x80x9cJNI 2 #3 #2xe2x80x9d stored in the vector memory address #1 indicates that the sequence control instruction of the address #3 is xe2x80x9cJNI 2xe2x80x9d, and the instruction of the address #2 should be output twice. The compressed instruction xe2x80x9cJNI 1 #5 #2xe2x80x9d stored in the vector memory address #2 indicates that the sequence control instruction of the address #5 is xe2x80x9cJNI 1xe2x80x9d, and the instruction of the address #2 should be output. The compressed instruction xe2x80x9cSTOP #6xe2x80x9d stored in the vector memory address #3 indicates that the sequence control instruction of the address #6 is xe2x80x9cSTOPxe2x80x9d.
FIG. 5 shows instructions transferred from the vector memory 12 to the bank memories 16A and 16C. The sequence control instructions may include a plurality of loops as shown in FIG. 4. Expanding the plurality of loops into successive instructions may delay the generation of the address signal 102. Therefore, the read out controller reads out the compressed instructions stored in the vector memory 12 and expands the read out compressed instructions to be transferred to the bank memories 16A and 16B. As is understood from FIGS. 4 and 5, the instruction of the outside loop xe2x80x9cJNI 1 #5 #2xe2x80x9d is converted to a simple instruction xe2x80x9cJMP #5 #2xe2x80x9d indicating that the address of the instruction to be output jumps to the address #2 at the address #5. The instruction of the inside loop xe2x80x9cJNI 2 #5 #2xe2x80x9d is converted to two separated instructions. When the instruction xe2x80x9cJMP #5 #2xe2x80x9d is input, the address expander 22 outputs the instruction of the address #2. Because the instruction of the address #2 is xe2x80x9cNEXTxe2x80x9d, the instruction of the address #3 xe2x80x9cJNI 2 #3 #2xe2x80x9d is output as the address signal 102.
FIG. 6 shows the operation to generate the test patterns based on the compressed instructions shown in FIG. 4. The compressed instructions stored in the vector memory 12 are expanded and transferred to the bank memories 16A and 16C. The address expander 22 generates the address signal 102 in accordance with the instructions expanded in the bank memories 16A and 16C and outputs the address signal 102 to the pattern former 26. In this embodiment shown in FIG. 6, the maximum value of the XB register is #3. When the value of the XB register exceeds #3, the value becomes #0. The effective value of the TP register is #FF (F means 15 out of 16 numbers or 15/16). The value of the TP register inverts within the effective number.
Firstly, the address expander 22 accepts the compressed instruction xe2x80x9cREPEAT 4 #1xe2x80x9d of the cache memory address #0 input from the bank memory 16A. The address expander 22, then repeatedly outputs the data of the address #1 4 times. The next compressed instruction is xe2x80x9cJNI 2 #3 #2xe2x80x9d, therefore the address expander 22 outputs the data of the address #2 and #3 in order. The address expander then repeatedly outputs the data from the address #2 and #3 twice in accordance with the compressed instruction xe2x80x9cJNI 2 #3 #2xe2x80x9d of the cache memory address #1 input from the bank memory 16A. The next compressed instruction is xe2x80x9cJMP #5 #2xe2x80x9d, which means that the sequence control instructions of the address #4 is xe2x80x9cNEXTxe2x80x9d. The address expander 22 then outputs the instruction of the address #4 and #5 in order. The address expander outputs the instruction of the memory address #2 in accordance with the compressed instruction xe2x80x9cJMP #5 #2xe2x80x9d of the cache memory address #2 input from the bank memory 16A. As the sequence control instruction of the address #2 is xe2x80x9cNEXTxe2x80x9d, the address expander 22 outputs the instruction of the address #3 in order. The next compressed instruction is xe2x80x9cJNI 2 #3 #2xe2x80x9d, so the address expander 22 outputs the sequence control instructions of the address #2 and #3 twice. The next compressed instruction is xe2x80x9cSTOP #6xe2x80x9d, which means that the sequence control instructions of the address #4 to the address #6 are xe2x80x9cNEXTxe2x80x9d and address expander 22 outputs the instruction of the address #4 to #6 in order. The test is then terminated.
The pattern former 26 accepts the address signal 102 from the sequence controller 62 and outputs the control instructions stored in each of the control memories 32a, 32b, and 32c. 
In the first cycle, the value of the address signal 102 is #0, therefore the XB register receives the address control instruction xe2x80x9cXB less than 0xe2x80x9d stored in the address #0 of the address control memory 32. The value of the XB register is set at #0 in this case. In the next cycle, the value of the address signal 102 is #1, therefore the address control instruction xe2x80x9cXB less than XB+1xe2x80x9d is read out from the address control memory 32a and the pattern former 26 adds 1 to the value of the XB register. This results in the value of the XB register becoming #0+1=#1. The address signal 102 having a value #1 is repeatedly output 3 times. The pattern former 26 adds 1 to the value of the XB register each time the address signal 102 having the value #1 is output. When the value of the XB register is #3 and the value 1 is added to the XB register, the value of the XB register becomes #0.
In the next cycle, the address signal 102 having the value #2 is output. Following this the address control instruction xe2x80x9cXB less than XBxe2x80x9d is read out from the address control memory 32a. The pattern former 26 keeps the value of the XB register at #0 as this is in accordance with the address control instruction xe2x80x9cXB less than XBxe2x80x9d. In the next cycle, the address signal 102 having the value #3 is output. The address control instruction xe2x80x9cXB less than XB+1xe2x80x9d is therefore read out from the address control memory 32a and the value of the XB register becomes #1. The address control instructions are read out from the address control memory 32a in accordance with the values of the address signal 102, in order. The test pattern calculator 36 generates the address pattern signals 106 in accordance with the address control instructions.
Similarly, the data control instructions are read out from the data control memory 32b and the value of the TP register is rewritten based on the data control instructions. When the address signal 102 whose data control instruction is xe2x80x9cTP less than 0xe2x80x9d is output, the data control instruction xe2x80x9cTP less than 0xe2x80x9d is read out from the data control memory 32b. The value of the TP register becomes #0. The result of this is the value of the data pattern signal 108 becomes #0. When the address signal 102 whose data control instruction is xe2x80x9cTP less than TPxe2x80x9d is output, the data control instruction xe2x80x9cTP less than TPxe2x80x9d is read out from the data control memory 32b. The value of the TP register is maintained as it is at this time. When the address signal whose data control instruction is xe2x80x9cTP less than /TPxe2x80x9d is output, the value of the TP register is inverted.
Similarly, when the address signal 102 is output, whose instruction stored in the read and write control memory is xe2x80x9cWxe2x80x9d, the instruction xe2x80x9cWxe2x80x9d is read out from the read and write control memory 32c. The test pattern calculator 36 outputs a read and write pattern signal 110 having the write cycle. When, on the other hand, the address signal 102 is output, whose instruction stored in the read and write control memory is xe2x80x9cRxe2x80x9d, the instruction xe2x80x9cRxe2x80x9d is read out from the read and write control memory 32c. The test pattern calculator 36 outputs a read and write pattern signal 110 having the read cycle. When the address signal 102 is output, whose instruction stored in the read and write control memory is xe2x80x9c/Dxe2x80x9d, the value of the TP register is inverted to be output as the data pattern signal 108. This means that the data pattern signal 108 becomes #FF when the value of the TP register is #0, and the data pattern signal 108 becomes #0 when the value of the TP register is #FF.
In FIG. 6 for example, the values of the address signal 102 from the second cycle to the fifth cycle are #1, therefore, the instruction xe2x80x9cWxe2x80x9d stored in the address #1 of the read and write control memory 32c is output 4 times. The W signal is output as the read and write pattern signal 110 at this time. In the sixth cycle, the value of the address signal 102 is #2, therefore the instruction xe2x80x9cRxe2x80x9d is read out from the read and write control memory 32c. The R signal is output as the read and write pattern signal 110. In the seventh cycle, the value of the address signal 102 is #3, therefore the read and write instruction xe2x80x9c/D Wxe2x80x9d is read out from the read and write memory 32c. The W signal is output as the read and write pattern signal 110 and the value of the data pattern signal 108 is inverted from #0 to #FF.
FIG. 7 shows another conventional semiconductor memory testing device capable of outputting address patterns at a high speed. Recently developed memory devices are operated at an extremely high frequency, making it difficult to generate address patterns at a high enough speed to allow testing of these memory devices by a single pattern former. Therefore a semiconductor memory testing device comprising a plurality of pattern formers is used to test these memory devices. The conventional semiconductor memory testing device shown in FIG. 7 comprises a plurality of pattern formers 26A and 26B to test a memory device operated with a high frequency. The pattern signals output from the plurality of pattern formers are simultaneously applied to the memory device 76. The sequence controller 62 shown in FIG. 7 is the same as the sequence controller shown in FIG. 1. The pattern formers 26A and 26B are the same as the pattern former 26 shown in FIG. 1. Therefore, the explanation will be omitted. The elements the same as the elements shown in FIG. 1 have the same marks and the explanation is therefore omitted.
FIG. 8 shows the instructions to be stored in the address control memory 32a of the pattern former 26A. The address control memory 32a comprises a normal field and an extended field. The instructions to go to the next address are stored in the normal field. The instructions not to go to the next address but to jump to other addresses are stored in the extended field. The data control memory 32b and the read and write control memory 32c respectively comprise normal fields and extended fields. This leads to the fact that the capacity of each of the memories 32a, 32b and 32c is required to be twice that of each of the control memories 32a, 32b and 32c shown in FIG. 1.
The instructions have been previously stored in the control memories 32 of the pattern formers 26A and 26B so that the desired address pattern signal 106, the data pattern signal 108, and the read and write pattern signal 110 are alternately generated by the pattern formers 26A and 26B. In the normal field of the address control memory 32a is stored an address control instruction obtained by combining two successive address control sequence instructions. For example, when the first address control sequence instruction xe2x80x9cXB less than 0xe2x80x9d and the second address control sequence instruction xe2x80x9cXB less than XB+1xe2x80x9d are combined, the value of the XB register becomes 1. Therefore, the instruction xe2x80x9cXB less than 1xe2x80x9d is stored in the normal field of the address control memory 32a. 
The value of the XB register becomes 2 based on the next two address control instructions xe2x80x9cXB less than XB+1xe2x80x9d and xe2x80x9cXB less than XB+1xe2x80x9d, therefore the instruction xe2x80x9cXB less than XB+2xe2x80x9d is stored in the normal field of the address control memory 32a. Similarly, the instructions xe2x80x9cXB less than XB+1xe2x80x9d, xe2x80x9cXB less than XB+1xe2x80x9d, and xe2x80x9cXB less than XB+1xe2x80x9d are stored in the normal field. Stored in the extended field of the address control memory 32a, are the address control instructions obtained by combining two address control instructions which are not executed in sequential order. For example, in FIG. 8, the seventh sequence instruction xe2x80x9cXB less than XB+1xe2x80x9d, should be executed after the eighth sequence instruction xe2x80x9cXB less than XBxe2x80x9d is executed. When these two instructions are executed, the value of the XB register increases by 1. Therefore, the instruction xe2x80x9cXB less than XB+1xe2x80x9d is stored in the address #3 of the extended field of the address control memory 32a. The seventh instruction xe2x80x9cXB less than XB+1xe2x80x9d should be executed after the tenth instruction xe2x80x9cXB less than XBxe2x80x9d is executed. When these two instructions are executed, the value of the XB register increases by 1. Therefore, the instruction xe2x80x9cXB less than XB+1xe2x80x9d is stored in the address #4 of the extended field of the address control memory 32a. 
FIG. 9 shows the data to be stored in the address control memory 32a of the pattern former 26B. The address control memory 32a of the pattern former 26B comprises a normal field and an extended field the same as the address control memory 32a of the pattern former 26A. The instructions to go to the next address are stored in the normal field. The instructions not to go to the next address but to jump to other addresses are stored in the extended field.
The combined address control instructions stored in the address control memory 32a of the pattern former 26A and the address control memory 32a of the pattern former 26B have different instructions. This means that the address control instructions stored in the address control memory 32a of the pattern former 26A should be obtained by combining the first and second address control instructions, and the third and fourth address control instructions of the address control sequence instruction. The address control instructions stored in the address control memory 32a of the pattern former 26B is same as the first address control instruction of the address control sequence instruction, obtained by combining the second and third address control instructions.
FIG. 10 shows a pattern program to be executed by the address expander 22 of the pattern generator shown in FIG. 7. One address signal 102 is generated by the pattern former 26A and the pattern former 26b, so the pattern program to be executed by the address expander becomes half. The pattern program should be set to obtain a desired pattern signal by taking the control instructions stored in the address control memories 32a and 32b of the pattern formers 26A and 26B. The pattern program is compressed for storage in the vector memory.
FIG. 11 shows an operational example of the pattern formers 26A and 26B shown in FIG. 7. The compressed instructions stored in the vector memory 12 are read out to the bank memories 16A and 16C in order and selected by the MUX 20 to be input to the address expander 22. The address expander 22 accepts the first compressed instruction xe2x80x9cJNI #3 #3 #3xe2x80x9d. When the address storing the first compressed instruction is #3, this means that the instruction xe2x80x9cNEXTxe2x80x9d is stored in the address #0, #1 and #2. The address expander 22 increases the value of the address signal 102 from 0 to 3. The value of the address #3 is output 3 times in accordance with the instruction xe2x80x9cJNI #3 #3 #3xe2x80x9d.
The value of the address signal varies by 0, 1, 2, 3, 3, 3, 3 as shown in FIG. 11. The address expander sets the value of the JFLG 104 as 1 when the value of the address is changed by the instruction xe2x80x9cJUMPxe2x80x9d. Otherwise, the value of the JFLG 104 becomes 0. The pattern former 26A outputs the address control instruction in accordance with the value of the address signal 102. At this time, the value of the extended field of the address control memory 32a is read out when the value of the JFLG 104 is 1, and the value of the normal field of the address control memory 32a is read out when the value of the JFLG 104 is 0.
The test pattern calculator 36 of the pattern former 26A changes the value of the XB register based on the address control instruction read out from the address control memory 32a and outputs the changed value. The test pattern calculator 36 of the pattern former 26B reads out the address control instruction from the address memory 32a in accordance with the address signal 102 and outputs the value. The value of the XB register of the pattern former 26B changes in accordance with the address control instruction read out from the address control memory 32a of the pattern former 26B. The high speed converter 30, shown in FIG. 7, selects either of the pattern formers 26A or 26B to output the signal. The address pattern signal shown in FIG. 11 is thus obtained. The data pattern signal 108 and the read and write signal 110 are obtained similarly.
The semiconductor memory testing device shown in FIG. 7 is capable of outputting the address patterns at a high speed. However, the control memory 32 of the semiconductor memory testing device shown in FIG. 7 is required to have a large capacity because when the instruction is xe2x80x9cREPEAT uneven numbersxe2x80x9d, an additional instruction xe2x80x9cNEXTxe2x80x9d is required to be written after the instruction xe2x80x9cREPEAT uneven numbersxe2x80x9d. Furthermore, new control instructions obtained by combining two control instructions to be stored in each of the control memories 32, the sequence control instructions and the compressed instructions have to be designed to correspond to the new control instructions. The pattern program is so large that it was difficult to design the compressed instructions in consideration of the new control instructions.
Therefore, it is an object of the present invention to provide a test pattern generator, a memory testing device, and a method of generating a plurality of test patterns which overcomes the above issues in the related art. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
In order to solve the above-stated problem, the present invention provides a test pattern generator for generating a plurality of test patterns to test a memory comprising: a control memory for storing a plural kinds of control instructions to generate the test patterns; a vector memory for storing vector instructions indicating an order of the control instructions to be read out from the control memory; a plurality of bank memories for storing the vector instructions read out from the vector memory, the bank memories alternatively storing the vector instructions; an address expander for generating an address of each of the control instructions in the control memory in accordance with the vector instructions stored in the plurality of bank memories; and a test pattern calculator for generating the test patterns based on the control instructions read out from an address generated by the address expander stored in the control memory.
Moreover, the present invention provides a test pattern generator for generating a plurality of test patterns to test a memory comprising: a control memory for storing a plural kinds of control instructions to generate the test patterns; a vector memory for storing vector instructions indicating an order of the control instructions to be read out from the control memory; a plurality of bank memories for storing the vector instructions read out from the vector memory; an address expander for generating an address of each of the control instructions in the control memory in accordance with the vector instructions stored in the plurality of bank memories; and a test pattern calculator for generating the test patterns based on the control instructions read out from an address generated by the address expander stored in the control memory.
Each of the vector instructions read out from the vector memory may be stored in each of the plurality of bank memories in order. The address expander may read out the vector instructions stored in the plurality of bank memories at the same time to generate an address of the control instructions in the control memory.
The test pattern calculator may comprise: sub test patterns based on the control instructions read out from the address of one of the sub control memories generated by the address expander, the sub test patterns being a part of the test patterns; and a high speed converter for generating the test patterns by outputting the sub test patterns from pattern calculators.
The control memory may comprise a plurality of sub control memories storing substantially same control instructions. The address expander may read out the vector instructions stored in the vector memory to generate an address of the control instructions in each of the plurality of sub control memories in order, for each of the plurality of sub control memories.
The control memory may comprise a plurality of sub control memories, each of the sub control memories storing a control instruction for generating a new test pattern based on an earlier test pattern generated at least two cycles ahead of the new test pattern. The address expander may read out the vector instructions stored in the vector memory to generate an address of the control instructions in each of the plurality of sub control memories in order, for each of the plurality of sub control memories.
Moreover, the present invention provides a test pattern generator for generating a plurality of test patterns to test a memory comprising: a plurality of control memories storing substantially same control instructions to generate the test patterns; a vector memory for storing vector instructions indicating an order of the control instructions to be read out from the plurality of sub control memories; an address expander for generating an address of each of the control instructions in each of the sub control memories for each of the sub control memories in accordance with the vector instructions stored in the vector memory; and a test pattern calculator for generating the test patterns based on the control instructions stored in the plurality of sub control memories indicated by the address generated by the address expander.
The plurality of sub control memories may store substantially same control instructions to generate a new test pattern based on an earlier test pattern generated at least two cycles ahead of the new test pattern.
The test pattern generator may further comprise a vector cache memory for storing the vector instructions read out from the vector memory, wherein the address expander generates an address of the control instructions in the plurality of sub control memories in accordance with the vector instructions stored in the vector cache memory.
The vector cache memory may comprise a plurality of bank memories for storing the vector instructions read out from the vector memory, each of the bank memories storing each of the vector instructions in order. The address expander may generate the address of the control instructions in the plurality of sub control memories in accordance with the vector instructions stored in the vector cache memory.
The vector cache memory may comprise a plurality of bank memories for storing the vector instructions read out from the vector memory. The address expander may generate the address of the control instructions in the plurality of sub control memories in accordance with the vector instructions stored in the vector cache memory.
The test pattern calculator may comprises: sub test patterns based on the control instructions read out from the address of one of the sub control memories generated by the address expander, the sub test patterns being a part of the test patterns; and a high speed converter for generating the test patterns by outputting the sub test patterns from pattern calculators.
Moreover, the present invention provides a test pattern generator for generating a plurality of test patterns to test a memory in a predetermined order comprising: a plurality of sub control memories each storing a control instruction for generating a new test pattern based on an earlier test pattern generated at least two cycles ahead of the new test pattern, a vector memory for storing vector instructions indicating an order of the control instructions to be read out from the plurality of sub control memories; an address expander for generating an address of each of the control instructions in each of the sub control memories for each of the sub control memories in accordance with the vector instructions stored in the vector memory; and a test pattern calculator for generating the test patterns based on the control instructions stored in the plurality of sub control memories indicated by the address generated by the address expander.
The plurality of sub control memories may store substantially same control instructions to generate a new test pattern based on an earlier test pattern generated at least two cycles ahead of the new test pattern.
The test pattern generator may further comprise a vector cache memory for storing the vector instructions read out from the vector memory, wherein the address expander generates an address of the control instructions in the plurality of sub control memories in accordance with the vector instructions stored in the vector cache memory.
The vector cache memory may comprise a plurality of bank memories for storing the vector instructions read out from the vector memory, each of the bank memories storing each of the vector instructions in order. The address expander may generate the address of the control instructions in the plurality of sub control memories in accordance with the vector instructions stored in the vector cache memory.
The vector cache memory may comprise a plurality of bank memories for storing the vector instructions read out from the vector memory. The address expander may generate the address of the control instructions in the plurality of sub control memories in accordance with the vector instructions stored in the vector cache memory.
The test pattern calculator may comprises: sub test patterns based on the control instructions read out from the address of one of the sub control memories generated by the address expander, the sub test patterns being a part of the test patterns; and a high speed converter for generating the test patterns by outputting the sub test patterns from pattern calculators.
Moreover, the present invention provides a memory testing device for testing electrical characteristic of a memory by comparing an output signal output from the memory when a predetermined signal is input to the memory with an expected signal output from a normal memory when the predetermined signal is input to the normal memory comprising: a control memory for storing a plural kinds of control instructions to generate a plurality of test patterns including the input signal and the expected signal; a vector memory for storing vector instructions indicating an order of the control instructions to be read out from the control memory; a plurality of bank memories for storing the vector instructions read out from the vector memory, each of the bank memories storing each of the vector instructions in order; an address expander for generating an address of each of the control instructions in the control memory in accordance with the vector instructions stored in the plurality of bank memories; a test pattern calculator for generating the test patterns based on the control instructions stored in the control memory indicated by the address generated by the address expander; a pin data selector for changing the test patterns generated by the test pattern calculator so as to correspond to pin arrangements of the memory; a waveform generator for generating the test patterns changed by the waveform generator; a memory acceptor comprising a memory slot to accept the memory, applying the test patterns generated by the waveform generator to the memory, and receiving the output signal output from the memory; and a comparing unit for judging whether or not the memory is normal by comparing the output signal received by the memory acceptor with the expected signal output from the pin data selector.
Moreover, the present invention provides a memory testing device for testing electrical characteristic of a memory by comparing an output signal output. from the memory when a predetermined signal is input to the memory with an expected signal output from a normal memory when the predetermined signal is input to the normal memory comprising: a control memory for storing a plural kinds of control instructions to generate a plurality of test patterns including the input signal and the expected signal; a vector memory for storing vector instructions indicating an order of the control instructions to be read out from the control memory; a plurality of bank memories for storing the vector instructions read out from the vector memory; an address expander for generating an address of each of the control instructions in the control memory in accordance with the vector instructions stored in the plurality of bank memories; a test pattern calculator for generating the test patterns based on the control instructions stored in the control memory indicated by the address generated by the address expander; and a memory acceptor applying the test patterns generated by the test pattern calculator to the memory, and receiving the output signal output from the memory.
Each of the vector instructions read out from the vector memory may be stored in each of the plurality of bank memories in order. The address expander may read out the vector instructions stored in the plurality of bank memories at the same time to generate an address of the control instructions in the control memory.
The test pattern calculator may comprise: sub test patterns based on the control instructions read out from the address of one of the sub control memories generated by the address expander, the sub test patterns being a part of the test patterns; and a high speed converter for generating the test patterns by outputting the sub test patterns from pattern calculators.
The control memory may comprise a plurality of sub control memories storing substantially same control instructions. The address expander may read out the vector instructions stored in the vector memory to generate an address of the control instructions in each of the plurality of sub control memories in order, for each of the plurality of sub control memories.
The control memory may comprise a plurality of sub control memories, each of the sub control memories storing a control instruction for generating a new test pattern based on an earlier test pattern generated at least two cycles ahead of the new test pattern. The address expander may read out the vector instructions stored in the vector memory to generate an address of the control instructions in each of the plurality of sub control memories in order, for each of the plurality of sub control memories.
Moreover, the present invention provides a memory testing device for testing electrical characteristics of a memory by comparing an output signal output from the memory when a predetermined signal is input to the memory with an expected signal output from a normal memory when the predetermined signal is input to the normal memory comprising: a plurality of sub control memories for storing a plural kinds of control instructions to generate a plurality of test patterns including the input signal and the expected signal, the plurality of sub control memories storing substantially same control instructions; a vector memory for storing vector instructions indicating an order of the control instructions to be read out from the plurality of control memories; an address expander for generating addresses of the control instructions in each of the plurality of sub control memories for each of the plurality of sub control memories in accordance with the vector instructions stored in the vector memory; a test pattern calculator for generating the test patterns based on the control instructions stored in the plurality of sub control memories indicated by the address generated by the address expander; and a memory acceptor applying the test patterns generated by the test pattern calculator to the memory, and receiving the output signal output from the memory.
Moreover, the present invention provides a memory testing device for testing electrical characteristics of a memory by comparing an output signal output from the memory when a predetermined signal is input to the memory with an expected signal output from a normal memory when the predetermined signal is input to the normal memory comprising: a control memory for storing a plural kinds of control instructions to generate a plurality of test patterns including the input signal and the expected signal; a plurality of sub control memories for storing a control instruction for generating a new test pattern based on an earlier test pattern generated at least 2 cycles ahead of the new control instruction; a vector memory for storing vector instructions indicating an order of the control instructions to be read out from the plurality of control memories; an address expander for generating addresses of the control instructions in each of the plurality of sub control memories for each of the plurality of sub control memories in accordance with the vector instructions stored in the vector memory; a test pattern calculator for generating the test patterns based on the control instructions stored in the plurality of sub control memories indicated by the address generated by the address expander; and a memory acceptor applying the test patterns generated by the test pattern calculator to the memory, and receiving the output signal output from the memory.
The plurality of sub control memories may store substantially same control instructions to generate a new test pattern based on an earlier test pattern generated at least two cycles ahead of the new test pattern.
The test pattern generator may further comprise a vector cache memory for storing the vector instructions read out from the vector memory, wherein the address expander generates an address of the control instructions in the plurality of sub control memories in accordance with the vector instructions stored in the vector cache memory.
The vector cache memory may comprise a plurality of bank memories for storing the vector instructions read out from the vector memory, each of the bank memories storing each of the vector instructions in order. The address expander may generate the address of the control instructions in the plurality of sub control memories in accordance with the vector instructions stored in the vector cache memory.
The vector cache memory may comprise a plurality of bank memories for storing the vector instructions read out from the vector memory. The address expander may generate the address of the control instructions in the plurality of sub control memories in accordance with the vector instructions stored in the vector cache memory.
The test pattern calculator may comprises: sub test patterns based on the control instructions read out from the address of one of the sub control memories generated by the address expander, the sub test patterns being a part of the test patterns; and a high speed converter for generating the test patterns by outputting the sub test patterns from pattern calculators.
Moreover, the present invention provides a method for generating a plurality of test patterns to test a memory, comprising: a first storing step of storing a plural kinds of control instructions to generate the test patterns into a control memory; a reading out step of reading out the control instructions from a vector memory storing vector instructions indicating an order of the control instructions to be read out from the control memory; a second storing step of storing the vector instructions read out from the vector memory into a plurality of bank memories, the vector instructions being alternately stored into the bank memories; an address generating step of generating an address of each of the control instructions in the control memory in accordance with the vector instructions stored in the plurality of bank memories; and a pattern generating step of generating the test patterns based on the control instructions, indicated by the address and stored in the control memory.
Moreover, the present invention provides a method for generating a plurality of test patterns to test a memory, comprising: a first storing step of storing a plural kinds of control instructions to generate the test patterns into a control memory; a reading out step of reading out the control instructions from a vector memory storing vector instructions, indicating an order of the control instructions to be read out from the control memory; a second storing step of storing the vector instructions read out from the vector memory into a plurality of bank memories; an address generating step of generating an address of each of the control instructions in the control memory in accordance with the vector instructions stored in the plurality of bank memories; and a pattern generating step of generating the test patterns based on the control instructions indicated by the address and stored in the control memory.
The second storing step may store each of the vector instructions read out from the vector memory into each of the plurality of bank memories in order. The address generating step may generate an address of the control instructions in the control memory in accordance with the vector instructions stored in the plurality of bank memories at the same time.
The test pattern step may comprise steps of: generating sub test patterns based on the control instructions read out from the address of one of the sub control memories generated by the address expander, the sub test patterns being a part of the test patterns; and generating the test patterns by outputting the sub test patterns.
The control memory may comprise a plurality of sub control memories storing substantially same control instructions. The address generating step may generate an address of the control instructions in each of the plurality of sub control memories in order for each of the plurality of sub control memories.
The control memory may comprise a plurality of sub control memories, each of the sub control memories storing a control instruction for generating a new test pattern based on an earlier test pattern generated at least two cycles ahead of the new test pattern. The address generating step may generate an address of the control instructions in each of the plurality of sub control memories in order for each of the plurality of sub control memories.
Moreover, the present invention provides a method for generating a plurality of test patterns to test a memory, comprising: a storing step of storing substantially same instructions into a plurality of sub control memories storing to generate the test patterns; a read out step of reading out vector instructions indicating an order of the control instructions to be read out from the plurality of sub control memories from the vector memory; an address generating step of generating an address of each of the control instructions in each of the sub control memories for each of the sub control memories in accordance with the vector instructions stored in the vector memory; and a test pattern generating step of generating the test patterns based on the control instructions stored in the plurality of sub control memories indicated by the address.
Moreover, the present invention provides a method for generating a plurality of test patterns to test a memory, comprising: a storing step of storing a control instruction for generating a new test pattern based on an earlier test pattern generated at least two cycles ahead of the new test pattern into a plurality of sub control memories; a reading out step of reading out vector instructions stored in a vector memory and indicating an order of the control instructions to be read out from the plurality of sub control memories; an address generating step of generating an address of each of the control instructions in each of the sub control memories for each of the sub control memories in accordance with the vector instructions stored in the vector memory; and a test pattern generating step of generating the test patterns based on the control instructions stored in the plurality of sub control memories indicated by the address.
The storing step may generate substantially same control instructions to generate a new test pattern based on an earlier test pattern generated at least two cycles ahead of the new test pattern into the plurality of sub control memories.
The read out step may store the vector instructions read out from the vector memory into avector cache memory. The address generating step may generate an address of the control instructions in the plurality of sub control memories in accordance with the vector instructions stored in the vector cache memory.
The vector cache memory may comprise a plurality of bank memories for storing the vector instructions read out from the vector memory, each of the bank memories storing each of the vector instructions in order. The address generating step may generate an address of the control instructions in the plurality of sub control memories in accordance with the vector instructions stored in the vector cache memory.
The vector cache memory my comprise a plurality of bank memories for storing the vector instructions read out from the vector memory. The address generating step may generate an address of the control instructions in the plurality of sub control memories in accordance with the vector instructions stored in the vector cache memory.
The test pattern step may comprise steps of: generating sub test patterns based on the control instructions read out from the address of one of the sub control memories generated by the address expander, the sub test patterns being a part of the test patterns; and generating the test patterns by outputting the sub test patterns.
This summary of the invention does not necessarily describe all necessary features. The invention may also be a sub-combination of these described features.